AMD Genoa processor
We’ve known for a long time that AMD will break the 64-core barrier in its AMD EPYC server CPUs with Zen 4, but the latest rumors that have surfaced have given us a much higher figure than initially expected. What do these rumors say about the number of cores in AMD EPYC Genoa, and how spectacular will the jump from AMD EPYC Milan be?
We have said it many times, the jump to DDR5 in combination with PCI Express 5.0 requires profound changes in the internal circuitry of the new CPUs, this means the update on the one hand of all the circuitry dedicated to communication with the memory on the one hand and that of peripherals on the other. Which incidentally leads to the adoption of new sockets and chipsets by both Intel and AMD.
How many cores will AMD EPYC Genoa have?
The information is not official from AMD but comes from AdoredTV. What do we know about AMD EPYC Genoa so far? Officially that it will be released in 2022 under the commercial name AMD EPYC 7004. If we look at the roadmap of AMD itself that was leaked a few days ago, in addition to the confirmation that it will have more than 64 cores, AMD will break that barrier.
The new information? Well, we have two contradictory sources. On the one hand, the Executable Fix insider talks about a 96-core configuration, while AdoredTV claims that the number of cores could go up to 128. We are not sure which of the two is correct, and it will be AMD that has the last word.
At the moment in the AMD EPYC range, the number of memory channels has always been proportional to the number of CCD chiplets, both in Zen 2 and Zen 3. We cannot forget that DDR5 is a dual-channel memory, and the famous 8 DDR4 memory channels are 16 channels in DDR5, hence possibly the 128 cores that AdoredTV claims. Bear in mind that the information speaks of 12 channels of DDR5 memory and not 16.
Let’s not forget that the coincidence between the number of RAM channels and the number of CCD Chiplets in the current AMD EPYC is nothing more than a coincidence, so it should not be confused as causality for the number of cores of these processors.
What other news will AMD EPYC Genoa bring?
The most important is the adoption of Zen 4, which will come in CCD chipsets such as Zen 2 and Zen 3 but built under TSMC’s 5 nm node and with the improved architecture to offer increases in the IPC above 20%.
Another significant change in Zen 4? The adoption of the AVX-512 instruction set that is exclusive to Intel and has been vital for specific contracts for this type of processor.
The only change that we are not going to see is in terms of the number of cores, which will continue to be 8 per CCD Chiplet , so the step to 5 nm will not be used to increase the number of cores but to improve these. As for adopting a hybrid architecture in the style of the CPUs with current ISA ARM or the imminent Alder Lake of Intel, we will have to wait until Zen 5.
Genoa processors will have a maximum of 96 Zen 4 processor cores and a 12/24 channel DDR5 memory controller.
In our previously reported RansomEXX cyberattack, up to 112 gigabytes of Gigabyte documents were stolen, some of which included documents subject to the confidentiality of AMD, Intel and AmericanMegatrends.
Now, the documentaries have also been released and are accompanied by AMD support documents for future Genoa processors on Zen 4 architecture. Genoa processors are compatible with the new LGA-type SP5 processor base.
The support documents for the leaked version 0.71 are dated July of this year. At the same time, they reinforce numerous rumors, such as a maximum of 12 processor chips. The basic structure of the processor chips remains familiar, even if the architecture changes; eight Zen 4 cores that share a common L3 level cache. So a Genoa processor can now have a total of 96 Zen 4 cores, which, according to leaked documents, now also support AVX-512 plugins. Although the Zen 4 processor chips are manufactured using TSMC’s 5-nanometer manufacturing process, their physical size is close to today’s Zen 3 cores.
The new IO chip now includes a 12/24 channel DDR5 memory controller and consumes up to 75% of the processor’s TDP in the worst case. 12/24 is explained by the fact that in DDR5 memories, instead of a 64-bit one (with 72-bit ECC), two 32-bit channels (with 40-bit ECC) are running on the same comb. However, channels are talked about as an old habit as if they were. Each channel or pair of channels can be expanded as usual with two memory locations. The manufacturing process for the IO chip is currently unknown, but it is not the same on TSMC N5 as it is on processor chips.
Genoa’s maximum TDP value clearly increases compared to previous generations. Where the TDP of the Milan processors of the Zen 3 generation reached a maximum of 280 watts, it reaches Genoa up to 400 watts. The minimum TDP value is 155 watts and the IO chip consumes 116-124 watts depending on the processor configuration. The maximum total power consumption of the processor can reach up to 700 watts for a maximum of one millisecond and 440 watts for 10 milliseconds.
The leak has also confirmed Chagall’s codename for future Zen 3 Threadripper processors, which also appeared on the roadmaps.